koulib@sh.itjust.works to Linux@lemmy.mlEnglish · 1 year agoWhich new Protocol or Standard are you most excited about?message-squaremessage-square48fedilinkarrow-up11arrow-down10file-text
arrow-up11arrow-down1message-squareWhich new Protocol or Standard are you most excited about?koulib@sh.itjust.works to Linux@lemmy.mlEnglish · 1 year agomessage-square48fedilinkfile-text
minus-squaresecret300@lemmy.sdf.orglinkfedilinkarrow-up0·1 year agoRISC-V I want open-source hardware
minus-squareRead Bio@lemm.eelinkfedilinkEnglisharrow-up0·edit-21 year agoImma stick with ARM and x64 ngl, ik it’s not open hardware but I don’t really mind that but cool to hear.
minus-square☆ Yσɠƚԋσʂ ☆@lemmy.mllinkfedilinkarrow-up0·edit-21 year agosome good news on that front https://github.com/OpenXiangShan/XiangShan
minus-squarepizzaboi@lemm.eelinkfedilinkEnglisharrow-up0·1 year agoIs there a good resource out there for wrapping my head around RISC-V? Last time I read a wiki my head hurt haha. Seems cool, though.
minus-squaredeur@feddit.nllinkfedilinkarrow-up0·edit-21 year agoIn principle it’s just “slimmer ARM”. RISC-V is also extremely dedicated to using memory mapped IO rather than older style IO x86_64 supports. Think lots of registers, a fun zero register that is always zero, and memory mapped IO.
minus-squaremvirts@lemmy.worldlinkfedilinkarrow-up0·1 year agoI for one think we need a register for each unsigned integer, why is zero so special? :P Or if we can’t get that, at least every power of 2 and power of 2 minus 1. Maybe I can submit a proposal for risc-VI 🤣
minus-squareporl@lemmy.worldlinkfedilinkEnglisharrow-up0·1 year agoI think a register for each of the primes should be enough.
minus-squarePetteriPano@lemmy.worldlinkfedilinkarrow-up0·1 year ago Maybe I can submit a proposal for risc-VI 🤣 No need! You can make your own custom extension! If the silicon doesn’t support it, then you can provide firmware to emulate it.
minus-squarecaseyweederman@lemmy.calinkfedilinkarrow-up0·1 year agoARM is also reduced-instruction set but I don’t know how they differ. Is the instruction set somehow more reduced?
minus-squareMonkderVierte@lemmy.mllinkfedilinkarrow-up0·1 year agoAren’t they more like a hybrid instruction set and architecture?
RISC-V
I want open-source hardware
Imma stick with ARM and x64 ngl, ik it’s not open hardware but I don’t really mind that but cool to hear.
some good news on that front https://github.com/OpenXiangShan/XiangShan
Is there a good resource out there for wrapping my head around RISC-V? Last time I read a wiki my head hurt haha. Seems cool, though.
In principle it’s just “slimmer ARM”. RISC-V is also extremely dedicated to using memory mapped IO rather than older style IO x86_64 supports.
Think lots of registers, a fun zero register that is always zero, and memory mapped IO.
I for one think we need a register for each unsigned integer, why is zero so special? :P
Or if we can’t get that, at least every power of 2 and power of 2 minus 1.
Maybe I can submit a proposal for risc-VI 🤣
I think a register for each of the primes should be enough.
No need! You can make your own custom extension! If the silicon doesn’t support it, then you can provide firmware to emulate it.
ARM is also reduced-instruction set but I don’t know how they differ. Is the instruction set somehow more reduced?
Aren’t they more like a hybrid instruction set and architecture?